Conventional video camera circuits with high dynamic range processing capabilities store data of one or more video frames to a dynamic random access memory. The data is subsequently read from the memory and distributed to multiple image processor pipeline sections simultaneously, with varying skews across the pipeline sections. Typical low power camera systems are designed to reduce the number of accesses to the memory to conserve power. Wearable high performance camera systems are designed to reduce the number of accesses to the memory to conserve memory bandwidth.
It would be desirable to implement data unit feed synchronization to multiple pipelines.